Control Systems

On the Mapping of Incremental Redundancy into a Physical Layer ASIC
Incremental Redundancy (IR) was introduced in GSM/EDGE and later adopted in Evolved EDGE in order to keep the throughput at an acceptable level. Legacy 2G networks with their ubiquitous coverage are apt to provide a fallback solution for the latest LTE networks. On the other hand, they provide a reliable data link for emerging M2M or IoT applications. IR data processing and controlling is speci...


Controllability of Linear Systems on Low Dimensional Nilpotent and Solvable Lie Groups
This paper is devoted to the study of controllability of linear systems on solvable and nilpotent Lie groups. Some general results are stated and used to completely characterize the controllable systems on the nilpotent Heisenberg group and the solvable two-dimensional affine group.
The τ Decomposition Method for PID Controllers of First Order Delayed Unstable Processes
The stabilization of first-order delayed (FOD) unstable processes with proportional–integral–derivative (PID) controllers is considered, and all the feasible PID controllers are determined. Different from the existing results which are based on the D-partition technique and partitioning complex's real and imaginary parts, a novel procedure enlightened by the τ decomposition method is propo...


Guaranteed estimates of the domain of attraction for a class of hybrid systems
This paper addresses the estimation of the domain of attraction for a class of hybrid nonlinear systems where the state space is partitioned into several regions. Each region is described by polynomial inequalities, and the union of all the regions is a complete cover of the state space. The system dynamics are defined on each region independently from the others by polynomial functions. First,...
A 6.13 $mu{rm W}$ and 96 dB CMOS Exponential Generator
In this brief, a new low-voltage CMOS circuit to produce current-mode exponential characteristics is proposed. MOSFET transistors in weak-inversion region and translinear principle for the temperature cancellation were used. The functionality of the proposed design confirmed with 0.35 $mu{rm m}$ CMOS process technology using ${pm}{rm 0.75}~{rm V}$ supply voltage. demonstrate the theoretical...


An Algorithm-Centric Energy-Aware Design Methodology
The goal of this brief is to present a unique top-down design methodology for developing energy-aware algorithms based on energy profiling. The key idea revolves around identifying and measuring components of code with high energy consumption. There are two major contributions of this brief: 1) a method for identifying components with high energy consumption in compute-intensive applications. T...
Low-Power Diagnostic Test Sets for Transition Faults Based on Functional Broadside Tests
Functional broadside tests address overtesting due to high-power dissipation by creating functional operation conditions during the clock cycles where delay faults are detected. Guided by their switching activity, it is possible to generate a low-power test set whose switching activity does not exceed the switching activity possible during functional operation. This brief applies the same appro...

Single-Port SRAM-Based Transpose Memory With Diagonal Data Mapping for Large Size 2-D DCT/IDCT
This brief describes a new method to implement the single-port SRAM-based transpose memory for large size discrete cosine transform (DCT)/indiscrete cosine transform (IDCT) which are used in the latest video coding standard, such as high efficiency video coding. Instead of shift-register array or multiport SRAM, only single-port SRAM is used in the proposed design. A new diagonal data mapping s...
Design and Implementation of Power-Efficient K-Best MIMO Detector for Configurable Antennas
In this brief, a power-efficient multiple-input multiple-output (MIMO) detector that can flexibly support multiple antenna configurations and modulations is presented. This detector uses a sorting-free K-best algorithm named distributed K-best (DKB) algorithm and successive interference cancellation (SIC) to decrease computational complexity. The DKB and SIC schemes are designed as several elem...

Runtime Self-Calibrated Temperature–Stress Cosensor for 3-D Integrated Circuits
On-chip temperature and stress sensors are important for runtime system management techniques tackling thermomechanical reliability issues in 3-D integrated circuits (ICs). However, traditional temperature and stress sensor designs require large calibration overhead to improve accuracy, which incurs significant cost for massive production. To address the challenge, in this paper, we propose a n...
A Reliability Enhanced Address Mapping Strategy for Three-Dimensional (3-D) NAND Flash Memory
The linear scaling down of NAND flash memory is approaching its physical, electrical, and reliability limitations. To maintain the current trend of increasing bit density and reducing bit per cost, 3-D flash memory is emerging as a viable solution to fulfill the ever-increasing demands of storage capacity. In 3-D NAND flash memory, multiple layers are stacked to provide ultrahigh density storag...

Low-Cost Post-Bond Testing of 3-D ICs Containing a Passive Silicon Interposer Base
Through-silicon vias (TSVs) provide high-density vertical interconnects between dies and enable the creation of 3-D ICs having higher performance and lower power consumption than traditional 2-D ICs. A practical TSV-based 3-D integration approach is to place multiple dies (or die stacks) side by side on a passive silicon interposer base, in which there are TSVs and metal wires serving as interc...
A Delay Test Architecture for TSV With Resistive Open Defects in 3-D Stacked Memories
The limits of technology scaling for smaller chip size, higher performance, and lower power consumption are being reached. For this reason, the memory semiconductor industry is searching for new technology. 3-D stacked memory using through-silicon via (TSV) has been considered as a promising solution for overcoming this challenge. However, to guarantee quality and yield for mass production of 3...
Power Blurring: Fast Static and Transient Thermal Analysis Method for Packaged Integrated Circuits and Power Devices
High-temperature and temperature nonuniformity in high-performance integrated circuits (ICs) can significantly degrade chip performance and reliability. Thus, accurate temperature information is a critical factor in chip design and verification. Conventional volume grid-based techniques, such as finite-difference and finite-element methods (FEMs), are computationally expensive. In an effort to ...
Fast RC Reduction of Flip-Chip Power Grids Using Geometric Templates
Realizable power grid reduction becomes a key to efficient design and verification of nowadays large-scale power delivery networks. Existing state-of-the-art realizable reduction techniques for interconnect circuits, such as the TICER algorithm, cannot be well suited for effective power grid reductions, since reducing the mesh-structured power grids by TICER's nodal elimination scheme may intro...